(kicad_pcb (version 4) (host pcbnew "(after 2015-may-01 BZR unknown)-product")
  (general
    (links 0)
    (no_connects 0)
    (area 60.143 125.153 103.727 144.827)
    (thickness 1.6)
    (drawings 0)
    (tracks 2)
    (zones 0)
    (modules 1)
    (nets 1)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (1 In1.Cu signal hide)
    (2 In2.Cu signal hide)
    (31 B.Cu signal)
    (33 F.Adhes user)
    (35 F.Paste user)
    (37 F.SilkS user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (47 F.CrtYd user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.635)
    (user_trace_width 0.19017)
    (user_trace_width 0.254)
    (user_trace_width 0.635)
    (user_trace_width 5.08)
    (trace_clearance 0.127)
    (zone_clearance 0.254)
    (zone_45_only yes)
    (trace_min 0.127)
    (segment_width 0.2)
    (edge_width 0.508)
    (via_size 0.4572)
    (via_drill 0.254)
    (via_min_size 0.4572)
    (via_min_drill 0.254)
    (user_via 0.635 0.4318)
    (uvia_size 0.4572)
    (uvia_drill 0.254)
    (uvias_allowed no)
    (uvia_min_size 0.4572)
    (uvia_min_drill 0.254)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1.5 1.5)
    (mod_text_width 0.15)
    (pad_size 0.127 1.004517)
    (pad_drill 0)
    (pad_to_mask_clearance 0)
    (pad_to_paste_clearance_ratio -0.15)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.150000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net_class Default "This is the default net class."
    (clearance 0.127)
    (trace_width 0.25)
    (via_dia 0.4572)
    (via_drill 0.254)
    (uvia_dia 0.4572)
    (uvia_drill 0.254)
  )
  (module gen:xxx (layer F.Cu) (tedit 55559503)
    (at 103.35 125.53)
    (fp_text reference A1 (at -27.29 5.52 180) (layer F.SilkS) hide)
    (fp_text value xxx (at -27.29 5.52 180) (layer F.Adhes) hide)
    (pad "" thru_hole circle (at -40.3 18.69) (size 5.08 5.08) (drill 3.175) (layers *.Cu *.Mask))
    (pad 42 smd oval (at -35.11 24.67) (size 0.127 1.004517) (layers F.Cu))
  )
)
